A logic gate circuit such as a DCFL (Direct Coupled FET Logic) circuit or a BFL (Buffered FET Logic) circuit, in which a drain of a load FET is connected to a high voltage power source (V.sub.DD), is available as a logic gate circuit such as an inverter or a NOR gate utilizing a junction FET or a MESFET.
A DCFL inverter circuit is shown in FIG. 24. In the figure, reference numeral 1 designates a switching FET, reference numeral 2 designates a load FET, reference numeral 5 designates an input terminal for a data signal, reference numeral 6 designates an output terminal for a data signal, reference numeral 7 designates a low voltage power source terminal, reference numeral 8 designates a high voltage power source terminal, and reference numeral 70 designates a switching FET of a next stage connected to the output terminal. The voltage of the high voltage power source and the voltage of the low voltage power source are designated as V.sub.DD and V.sub.SS, respectively. The switching FET1 is an enhancement type FET in which there is no current flowing between the drain and the source when the gate-source voltage is zero, and the load FET2 is a depletion type FET in which there is current flowing between the drain and the source even when the gate-source voltage is zero. The drain of the switching FET1 is connected to the source of the load FET2, which also serves as the output terminal. The gate of the load FET2 is connected to the source of the load FET2. Both FETs have n type channels.
The operation of this DCFL inverter circuit will be described with reference to the operation curve illustrated in FIG. 25. In the figure, the abscissa represents the voltage of the output terminal 6 and the ordinate represents the current flowing through the switching FET1, the load FET2, or the output terminal 6. For the low level signal voltage V.sub.L and the high level signal voltage V.sub.H in a digital circuit utilizing DCFL, the following relationship stands: V.sub.SS &lt;V.sub.L .ltoreq.V.sub.th1 &lt;V.sub.H .ltoreq.V.sub.DD, where V.sub.th1 designates the threshold voltage of the switching FET1, and if the voltage between the gate and the source is designated as V.sub.gs, then the current between the drain and the source does not flow when V.sub.gs .ltoreq.V.sub.th1, but does flow when V.sub.gs &gt;V.sub.th1. When the signal voltage at the input terminal 5 is high, the gate voltage of the switching FET1 becomes V.sub.H and it takes the on-state, that is, a state in which the current flows between the drain and the source in the FET1. The current-voltage characteristic between the drain and the source of the switching FET1 then becomes 80 in the figure. In the load FET2, since the voltage between the gate and the source is fixed as described above, its current-voltage characteristic between the drain and the source always remains 82 in the figure independently of the voltage at the input terminal. That is, the load FET2 serves as a source of constant current which maintains the current I.sub.L. Therefore, the operating point in this case becomes a point A which is the intersection of the curves 80 and 82 and the signal voltage at the output terminal 6 becomes V.sub.L, that is, the low signal voltage. When the signal voltage at the input terminal 6 is low, the gate voltage of the switching FET1 becomes V.sub.L and it takes the off-state, that is, a state in which no current flows between the drain and the source in the FET1. The current-voltage characteristic between the drain and the source of the switching FET1 then becomes 81 in the figure. Since the output terminal 6 is connected to the gate of the switching FET70 of the next stage and the current-voltage characteristic between the gate and the source of a junction FET or a MESFET presents a diode characteristic, when the voltage at the input terminal 6 increases beyond the rise voltage V.sub.F in the forward direction of this diode, a forward direction current shown by a curve 83 in the figure starts to flow through the output terminal 6. Since V.sub.DD is usually set such that V.sub.DD &gt;V.sub.F, the operating point in this case becomes a point B which is the intersection of the curves 82 and 83, and the signal voltage at the output terminal 6 becomes V.sub.H, that is, a high voltage. In either case, the dissipation current of the inverter circuit remains constant, showing a value I.sub.L.
When the signal voltage at the input terminal switches from high to low, the characteristic of the switching FET1 changes from 80 to 81 in FIG. 25. Therefore, the current I.sub.L of the load FET2 flows into the gate of the switching FET70 of the next stage through a wiring and until the voltage of the gate becomes high, that is, V.sub.H, the current continues to charge the capacitance between gate and source C.sub.gs of the next stage FET and the wiring capacitance C.sub.L. On the other hand, when the signal voltage at the input terminal switches from low to high, the characteristic of the switching FET1 changes from 81 to 80 in the FIG. 25. Therefore, the capacitance between gate and source C.sub.gs of the next stage FET and the wiring capacitance C.sub.L are discharged by the current corresponding to the difference between the current I.sub.L and the current represented by the curve 80 flowing from the gate of the next stage FET70 to the low voltage power source terminal 7 through the wiring and the switching FET1, and the gate voltage of the FET70, that is, the voltage at the output terminal 6 becomes low, that is, V.sub.L. The shorter the time required to charge/discharge the capacitance C.sub.gs of the next stage switching FET and the wiring capacitance C.sub.L becomes, the faster the operating speed of the logic gate circuit becomes (the shorter the delay time becomes). Therefore, if the capacitance C.sub.gs +C.sub.L which is connected to the output terminal is held constant, the larger the dissipation current I.sub.L becomes, the faster the operation speed of the logic gate circuit becomes. In this case, it is also necessary to set the current of the switching FET in the on-state to appropriate value with respect to I.sub.L.
If the gate length is held constant, the I.sub.L is determined by the gate width and the threshold voltage of the load FET. Since, in the fabrication of digital integrated circuits, the channels of load FETs are usually formed by ion implantation or the like, the threshold voltage cannot be varied for each FET but can only be set for several values for a wafer at the most. Therefore, the adjustment of the dissipation current for each logic gate circuit is achieved by adjusting the gate widths of the FET. However, there exists a minimum width W.sub.gmin for the gate width which is dependent on a production process and an FET having a gate width which is less than the minimum width W.sub.gmin cannot be fabricated.
Therefore, in designing a digital LSI, the gate width of an FET of a logic gate circuit whose required current is the least can be chosen to be the W.sub.gmin, and the threshold voltage of the load FET can be set so that the current required in this logic gate circuit is obtained.
However, in a digital LSI utilizing the prior art DCFL gate circuit described above, when the number of logic gate circuits whose required current is low is small and the majority of logic gate circuits of the LSI requires larger current, if only one threshold voltage is chosen for the load FETs, it becomes necessary to design the gate width of the FET to be bigger than W.sub.gmin and the logic gate circuit has a large dissipation current and the chip size of the LSI increases. For example, in the LSI illustrated in FIG. 26 having a high speed operating section (high power dissipation section) 91 and a low speed operating section (low power dissipation section) 92, since the required optimum current for each section is different, if the threshold voltage is set for a load FET in the low speed operating section 92, the gate width of an FET in the high speed operating section 91 increases, resulting in an increase in the chip size of the LSI. On the other hand, if the gate width of a load FET in the high speed operating section 91 is chosen to be W.sub.gmin and the threshold voltage is set for this load FET, the dissipation current (power dissipation) of the low speed operating section (low power dissipation section) 92 increases.